1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor device that includes a device formed in a semiconductor layer on an insulating film, and a method of manufacturing the same.
2. Background Information
Related examples of a semiconductor device that include an MOS transistor formed with a semiconductor process are described in Japanese Patent Publications JP-A-2000-150806 and JP-A-11-003992, which are hereby incorporated by reference.
Japanese Patent Publication JP-A-2000-150806 discloses a semiconductor device, which includes device-separation insulating films, an active region, a pseudo region, a gate electrode, a pseudo conductive film, and an interlayer insulating film. The device-separation insulating films are buried in trenches formed on a surface of a semiconductor substrate of a bulk. The active region and the pseudo region are separated by a device-separation insulating film on a surface of a semiconductor substrate. The gate electrode is formed on an active region. The pseudo conductive film is formed on a device-separation insulating film at almost the same height with a gate electrode. The interlayer insulating film covers the gate electrode and the pseudo conductive film. In the semiconductor device, the pseudo region inhibits occurrence of erosion, for which the active region is excessively polished, and of dishing, for which the insulating film in a trench is excessively polished at the middle.
The device-separation insulating film is formed by the following steps. That is, the device-separation insulating film is buried in trenches that are formed on a surface of the semiconductor substrate of the bulk, and then the insulating film is polished by the CMP method so that the insulating film remains only in the trenches. If the area of the active region is too small compared to the area of the trench in polishing the device-separation insulating film, there is a possibility that excessive of erosion may occur in the polish in the active region compared to the polish in the insulating film. Also, in polishing the device-separation insulating film that is buried in a wide trench, there is a possibility dishing might occur in the thickness of the device-separation insulating film as the middle gets thinner than at the edges.
Accordingly, the semiconductor device inhibits the occurrence of erosion and dishing by increasing the substantive area of the active region by forming a pseudo region and decreasing the area of the trench at the same time.
In addition, the pseudo-conductive film improves planarization of the interlayer insulating film. In conducting planarization of the interlayer insulating film that covers the gate electrode by polishing it with the CMP method, polishing speed highly depends on a difference of elevation of a substrate pattern. In a part that there are few gate electrodes, the difference of elevation in the substrate pattern enlarges and polishing speed in the interlayer insulating film varies inside the film because a gate electrode is a part that projects from an active region. Therefore, the difference in elevation in the substrate is reduced by making the part projecting from an active region dense by allocating a pseudo electrode that has a similar height with the gate electrode.
Japanese Patent Publication JP-A-11-003992 also discloses a semiconductor device in which a pseudo region (a dummy device region) and a pseudo conductive film (a dummy gate electrode) are formed, as described in Japanese Patent Publication JP-A-2000-150806. Furthermore, in the semiconductor device, a dummy electrode has an electrical interconnection with a pseudo region in order to prevent a state in which the dummy gate electrode is in a state of floating. To put it concretely, a part of the dummy gate electrode is formed on a pseudo region, and the dummy gate electrode and the pseudo region are connected by a titanium silicide layer.
By the way, in recent years, an MOS transistor can be manufactured with a Silicon on Insulator (SOI) substrate to reduce power consumption. Especially, power consumption is effectively reduced with a full depletion layer type SOI, which inhibits the short channel effect by making an SOI layer (a semiconductor layer on an insulating film) thin and is operated in a full depletion layer. In a full depletion layer type SOI, sheet resistance increases because thickness of an SOI layer is formed at 50 nanometers or less. Accordingly, R. Chau et al., in “A 50 nm depleted-substrates CMOS transistor (DST),” IEDM 2001, pp. 621–624, which is hereby incorporated by reference, describes a method of reducing sheet resistance by forming a source drain that is thicker than a channel layer by epitaxial growth of silicon in the source drain.
In conducting epitaxial growth of silicon on an extremely thin SOI layer, such as an SOI layer in a full depletion layer type SOI, silicon in the SOI layer agglutinates when epitaxial growth is conducted at a general growth temperature (e.g., 800 degrees C.). Therefore, epitaxial growth has to be conducted at a low temperature (e.g., 700 degrees C. or below) so that the SOI layer does not agglutinate. However, the inventor of the present invention found that growth rate depends more on the density of silicon that is exposed on a substrate pattern than other growth conditions such as gas concentration or pressure.
FIGS. 1(a) to 1(c) a diagrams illustrating a part with high pattern ratio of silicon and a part with low pattern ratio of silicon in a semiconductor wafer. Here, the pattern ratio of silicon means a proportion of an area of silicon that is exposed on a substrate to epitaxial growth of silicon to the total area of the substrate. A growth rate v is expressed in a formula v/v0, on the basis of the growth rate v/0 when the pattern ratio is 100%. FIG. 1(b) is a diagram illustrating a part with a high pattern ratio of silicon in the semiconductor wafer. The part surrounded by an outside rectangle shows the whole of a part with high pattern ratio of silicon in the semiconductor wafer. Further black parts show a part of silicon that is exposed. The pattern ratio of the part with a high pattern ratio is a proportion of the area of the black parts to the area of the whole of the part with the high pattern ratio surrounded by the outside rectangle. For example, the pattern ratio of the part with high pattern ratio of silicon is 80% or more. FIG. 1(c) is a diagram illustrating a part with a low pattern ratio of silicon in a semiconductor wafer. The part surrounded by an outside rectangle shows the whole of a part with a low pattern ratio of silicon in the semiconductor wafer. Further, the black part shows the part of silicon that is exposed. The pattern ratio in a part with low pattern ratio of silicon is a proportion of the area of a black part to the area of the whole of the part with a low pattern ratio surrounded by the outside rectangle. For example, the pattern ratio in a part with the low pattern ratio of silicon is 10% or less.
FIGS. 2(a) and 2(b) are charts illustrating a growth rate of silicon for the x-axis and the y-axis in low-temperature epitaxial growth. As shown in FIG. 1(a), horizontal axes, x and y in FIGS. 2(a) and 2(b), are used to show coordinates of the x-axis and y-axis arranged such that the middle of a wafer is set to be the origin. In both the x-axis and y-axis, a coordinate value on the edge of a part of that chip is formed to be set to one. In the charts, a measurement result in a part with high pattern ratio is obtained when the whole of the wafer is the part with high pattern ratio (pattern ratio is 80% or greater), and a measurement result in the part with a low pattern ratio is obtained when the whole of the wafer is a part with a low pattern ratio (pattern ratio is 10% or less). Also, in the measurement, the growth rate is measured by conducting epitaxial growth of silicon with a Vapor Phase Epitaxy (VPE) method. Epitaxial growth is conducted at 730 degrees C. of atmosphere temperature by using SiH2Cl2 as gas to grow silicon and HCl as a gas to conduct etching of silicon that adheres to a device-separation insulating film.
In reference to FIGS. 2(a) and 2(b), it is obvious that the growth rate in the low-temperature epitaxial growth of silicon decelerates in a part with a low pattern ratio of silicon (pattern ratio is 10% or less), compared to a part with a high pattern ratio of silicon (pattern ratio is 80% or more), when an identical process is used (i.e., when growth conditions such as gas used and atmosphere temperature are identical) and when growth rate is measured along the x-axis and y-axis.
Therefore, in conducting low-temperature epitaxial growth of silicon with the identical process, if the pattern ratio of silicon varies from place to place on an identical chip extra space, an identical wafer, or a plurality of wafers, that is, if the density of exposed silicon varies from place to place, the growth rate varies from place to place and the film thickness of the epitaxial layer is uneven because film thickness of the epitaxial layer is thicker in a part in which the density of exposed silicon is high than in a part in which the density of exposed silicon is low.
However, the problem of the growth rate in low-temperature epitaxial growth depending on the density of exposed silicon is described neither Japanese Patent Publications JP-A-2000-150806 and JP-A-11-003992, nor the nonpatent literature described above. Both Japanese Patent Publications JP-A-2000-150806 and JP-A-11-003992 describe a step of forming a pseudo conductive film and a pseudo region that are made of silicon. However, the pseudo conductive film makes a part that is projected from an SOI layer dense, and the pseudo region prevents a region of silicon in the SOI layer from being much smaller than that of a device-separation insulating film to inhibit occurrence of erosion and dishing in polishing a device-separation insulating film. Therefore, the pseudo conductive film and the pseudo region are not used to adjust the density of exposed silicon.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device and method of manufacturing the same. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.